1. Field of the Invention
The invention relates to an analog/digital converter, and more particularly proposes an analog/digital converter which scans analog voltages of plural channels to convert them into digital values.
2. Description of Related Art
FIG. 1 is a block diagram showing the configuration of a prior art analog/digital converter. An analog/digital control register (hereinafter, abbreviated as "A/D control register") 1 including group selection bits b.sub.0, b.sub.1, and b.sub.2 is connected to a data bus DB, and also to an analog/digital control circuit (hereinafter, abbreviated as "A/D control circuit") 2. The A/D control circuit 2 conducts controls such as selection of channels, one-shot scan mode, continuous scan mode, and output of an interrupt signal. Analog input terminals AN.sub.0 -AN.sub.7 of plural channels which are to be subjected to the analog/digital conversion are coupled to the one input terminal of a comparator 7 through a selector 8 which selects one of the analog input terminals.
A digital/analog converter (hereinafter, abbreviated as "D/A converter") 6 to which a reference voltage V.sub.ref, and ground potential V.sub.ss are applied outputs an analog voltage V.sub.AN. The analog voltage V.sub.AN is supplied to the ow}aid input terminal of the comparator 7. A comparison result which is an output of the comparator 7 is supplied to the A/D control circuit 2. The A/D control circuit 2 outputs a selection signal S.sub.SL for selecting one of analog voltages, and a comparison result signal S.sub.CP. The selection signal S.sub.SL is supplied to the selector 8, and the comparison result signal S.sub.CP to an analog/digital successive approximation register (hereinafter, abbreviated as "A/D successive approximation register") 5. The A/D successive approximation register 5 is connected to the D/A converter 6 and an analog/digital scan data register (hereinafter, abbreviated as "A/D scan data register") 3 which is a register for storing digital values that have been obtained by the A/D conversion in a scan mode.
The A/D successive approximation register 5 is connected also to the data bus DB so that data can be written into and read out from the register. The A/D scan data register 3 is connected to the data bus DB. Every time the A/D conversion or the scan operation is terminated, an analog/digital scan conversion termination interrupt signal (hereinafter, abbreviated as "A/D interrupt signal") S.sub.A is output.
Next, the operation of the analog/digital converter will be described with reference to FIG. 2 which shows contents of the scan mode.
An initial data is supplied through the data bus DB to the A/D successive approximation register 5, and written thereinto. The written initial data is then supplied to the D/A converter 6 which in turn compares in level a voltage due to the initial data with the reference voltage V.sub.ref, to convert the digital value into an analog voltage. The converted analog voltage V.sub.AN is supplied to the comparator 7.
In the case where, for example, "0", "0" and "0" are written into the A/D control register 1 including the group selection bits b.sub.0, b.sub.1, and b.sub.2, first, the A/D control circuit 2 reads out data of selected bits. The A/D control register 1 is designed so that either of data "0" or "1" is supplied to the group selection bits b.sub.0, b.sub.1, and b.sub.2. As shown in FIG. 2, the scan sequence is decided in accordance with the combination of the group selection bits b.sub.0, b.sub.1, and b.sub.2. As a result of reading out the data, the scan object channel is fixed to the same channel, and the selection signal S.sub.SL for selecting, for example, the analog input terminal AN.sub.0 is supplied to the selector 8. This causes the selector 8 to operate so as to select the analog input terminal AN.sub.0, and the analog voltage of the selected analog input terminal AN.sub.0 is supplied to the comparator 7.
Then the comparator 7 compares in level the analog voltage of the analog input terminal AN.sub.0 with the analog voltage V.sub.AN. The comparison result is supplied to the A/D control circuit 2, and the comparison result signal S.sub.CP from the control circuit is supplied to the A/D successive approximation register 5 to be stored thereinto. Data stored in the A/D successive approximation register 5 are supplied to the D/A converter 6. The D/A converter 6 compares in level a voltage due to the data with the reference voltage V.sub.ref, and the analog voltage V.sub.AN obtained as a result of the D/A conversion is supplied to the comparator 7. Then the comparator 7 compares the analog voltage V.sub.AN with the analog voltage of the analog input terminal AN.sub.0, and sends the comparison result to the A/D control 2. The comparison result signal S.sub.CP is again supplied from the A/D control circuit 2 to the A/D successive approximation register 5 to be stored thereinto.
The above-mentioned operation is repeated so that the analog voltage of the analog input terminal AN.sub.0 is converted into a digital value of a given bit number. After the conversion of the voltage into data of a given bit number is terminated, data stored in the A/D successive approximation register 5 are supplied to the A/D scan data register 3 to be stored thereinto. At the same time, the A/D control circuit 2 outputs the interrupt signal S.sub.A, and the selection signal S.sub.SL is extinguished so that the selector 8 enters the state where the analog input terminal AN.sub.0 is not selected.
Then the selection signal S.sub.SL is again supplied from the A/D control circuit 2 to the selector 8. The selector 8 selects the analog input terminal AN.sub.0, and the selected analog voltage is converted into a digital value of a given bit number in the same manner as described above. The digital value is stored into the A/D scan data register 3. In this way, in the case where "0", "0", and "0" are written into the A/D control register including the group selection bits b.sub.0, b.sub.1, and b.sub.2, the analog input terminal AN.sub.0 is repeatedly scanned, and a scanned analog voltage is converted into a digital value of a given bit number. Also in the case where "0", "0", and "1" are respectively written at the group selection bits b.sub.0, b.sub.1, and b.sub.2, the same operation is conducted.
When "0", "1", and "0" are written into the A/D control register including the group selection bits b.sub.0, b.sub.1, and b.sub.2, for example, a loop L.sub.2 is selected and a scan group Ga of the selected loop is selected so that the scan sequence is set to be the sequence of the analog input terminals AN.sub.0, AN.sub.1, and AN.sub.2. In the same manner as described above, this causes the analog input terminal AN.sub.0 to be first selected. The selected analog voltage is converted into a digital value of a given bit number, and the digital value is stored into the A/D scan data register 3.
Next, the selection signal S.sub.SL is changed so that the selector 8 selects the analog input terminal AN.sub.1. The analog voltage of the analog input terminal AN.sub.1 is converted into a digital value of a given bit number, and the digital value is stored into the A/D scan data register 3. The selection signal S.sub.SL is again changed so that the selector 8 selects the analog input terminal AN.sub.2. The analog voltage of the analog input terminal AN.sub.2 is converted into a digital value of a given bit number, and the digital value is stored into the A/D scan data register 3. At the time each scan operation is terminated, the A/D control circuit 2 outputs the interrupt signal S.sub.A.
As shown in FIG. 2, in the case where the contents of the A/D control register including the group selection bits b.sub.0, b.sub.1, and b.sub.2, are "1", "0", and "0", the scan operation is conducted in the sequence of the analog input terminals AN.sub.1 and AN.sub.2. Similarly, the scan operation is conducted in following sequences: the sequence of the analog input terminals AN.sub.4, and AN.sub.5 in the case of "1", "0", and "1"; the sequence of the analog input terminals AN.sub.0, AN.sub.1, and AN.sub.2 in the case of "0", "1", and "0"; the sequence of the analog input terminals AN.sub.4, AN.sub.5, and AN.sub.6 in tile case of "0", "1", and "1"; the sequence of the analog input terminals AN.sub.0, AN.sub.1, and AN.sub.2, and AN.sub.3 in the case of "1", "1", and "0"; and the sequence of the analog input terminals AN.sub.4, AN.sub.5, and AN.sub.6 and AN.sub.7 in the case of "1", "1", and "1". In other words, one of the seven kinds of the scan sequences of analog voltages can be selected depending on the value of the A/D control register including the group selection bits b.sub.0, b.sub.1, and b.sub.2.
Japanese Application Laid-Open No. 1-147618 (1989) discloses a similar analog/digital converter. FIG. 3 is a block diagram showing the configuration of the analog/digital converter. A priority channel register group 31 stores data for deciding the priority of channels to which a conversion request is issued in the scan mode. The priority channel register group 31 is connected to a register selector 34 which is connected to a signal selector 39 through a channel bus 38. A Conversion request circuit 32 consists of an autoscan register 32a, and a conversion request register 32b.
Registers of the priority channel register group 31 are connected in an arrangement corresponding to that of the autoscan register 32a of the conversion request circuit 32. The conversion request register 32b of the conversion request circuit 32 is connected to a priority decision circuit 33 which is connected through buses totaling m to the register selector 34. A termination signal is supplied to the conversion request circuit 32, and the priority decision circuit 33 outputs a conversion start signal. The priority channel register group 31, the register selector 34, the conversion request circuit 32, and the priority decision circuit 33 constitute a conversion control circuit 30. The conversion control circuit 30 is connected to a control bus 35, an address bus 36, and a data bus 37.
The analog/digital converter can decide the priority of the channels by means of the priority channel register group 31. In the autoscan register 32a of the conversion request circuit 32, the bits of channels to be subjected to the A/D conversion are previously set to be "1" by a CPU which is not shown. In the conversion request register 32b, an interrupt from the CPU takes place and the bits of channels to be subjected to the A/D conversion are set to be "1". The priority decision circuit 33 selects the bit of the highest priority from the preset bits set in the conversion request register 32b. The register selector 34 selects the register corresponding to the bit number which is selected by the priority decision circuit 33, and sends the selected bit number through the channel bus 38 to the signal selector 39.
The priority of the A/D conversion channels which are selected by the autoscan register 32a is previously set in the priority channel register group 31. A channel to be converted is set in the conversion request register by the priority decision circuit 33, and then subjected to the A/D conversion. When an interrupt takes place during a conversion of a channel of a low priority, generally, the priority decision circuit 33 refers to the priority channel register group 31 and sets the conversion request register so that the channel to which a conversion request is issued is converted. Then the conversion which is currently conducted is aborted and the conversion of a channel of a higher priority is conducted.
Japanese Application Laid-Open No. 1-147618 (1989) discloses also an analog/digital converter in which the degree of freedom of the input selection in the scan mode is realized. Japanese Application Laid-Open No. 1-174120 (1989) discloses an analog/digital converter in which the scan sequence is decided by using outputs of a counter and a shift register. Japanese Application Laid-Open No. 63262716 (1988) discloses an analog/digital converter which comprises a FIFO scan register for obtaining the degree of freedom of the selection of analog voltages, and a register for the conversion step number.
As described above, in the scan mode operation of the prior art analog/digital converter shown in FIG. 1, analog voltages are converted into digital values only in the scan sequence of the analog voltages which is decided for a selected scan group, and the scan sequence cannot be changed during the scan operation. In other words, the degree of freedom of the selection of analog voltages of plural channels is low.
In the analog/digital converter of FIG. 3 which is disclosed in Japanese Application Laid-Open No. 1147618 (1989), the pattern of the conversion sequence of temporary conversion requests is previously set, and therefore a priority channel register corresponding to the pattern is required so that the converter is enlarged in size and complicated in configuration. When the scan operation is to be conducted in a pattern other than the preset one, a complicated control is required.
The analog/digital converter disclosed in Japanese Application Laid-Open No. 1-174120 (1989) cannot cope with a process which is to be conducted in response to an interrupt for temporarily converting analog voltages, and requires the means for storing the scan patterns. The analog/digital converter disclosed in Japanese Application Laid-Open No. 63-262716 (1988) requires many registers.